Moore’s law is coming to an end – not only due to economic reasons – but even more so as on-chip dimensions reach atomic scale. To replace classic scaling, a large variety of novel device concepts have been proposed worldwide. In a hybrid integration with advanced CMOS circuits, these have the potential to enable further scaling. In the domains of re-configurable circuits or non-volatile memories, resistively switching devices are an interesting candidate potentially storing 2 or more states. On one side, their hybrid integration requires novel methodologies during design, simulation and optimization that respect the various technological requirements and constraints of such devices, their circuits and hybrid architectures. On the other side, the particular physical properties of the devices themselves, such as statistical fluctuations or coupling, demand novel circuit techniques for mitigation to satisfy the need for good reliability, minimal energy consumption and improved area efficiency. Here, feedback loops are employed to dynamically adapt circuit operation based on in-situ measurements in silicon. Moreover, neuromorphic concepts will be used in the future since principles such as adaptivity, sparsity and parallelism – analogous to the biological information processing in the brain – exhibit promising properties in order to address the aforementioned challenges.