As before, the objective is to conceive of new physical oriented design concepts of high energy and area efficiency. Application examples can be found in domains such as channel decoders, software-defined radios or machine learning.
Channel decoder are used for error detection and correction in various domains. One example is the high-throughput digital (wireless and wireline) transmission channels. Another one is found as key component of modern storage systems. The challenges are two-fold: on one side is the high computational throughput requirement, on the other side is the constraint on available area and acceptable cost. This is especially true Turbo- and Low-Density-Parity-Check-Codes with transmission rates close to the fundamental Shannon limit.
System-on-Chip-components for Multi-Radio support
Today, devices for wireless communication are required to support multiple standard simultaneously (such as GSM, UMTS, LTE, WLAN, BT, GPS) in order to limit the system integration complexity and cost. Classic highly optimized SoCs are not meeting these requirements anymore – especially in view of evolving standard within the lifetime of a product. The so-called “Software Defined Radio” concept offers such flexibility but poses enormous requirements on the available performance and communication bandwidth between the required, highly-parallel processing units realized in “Single Instruction Multiple Data” (SIMD) architectures. Here, flexible accelerators offer key advantages. Suitable micro-architectures and concepts for implementation are developed at the chair targeting low-power, area efficient arithmetic units. This includes macros for ‘Fast-Fourier-Transforms’ (FFT) and static (non-volatile) memories of small to medium capacity as required for such processing units.
In the domain of machine learning, significant advances are attributed to the success of Artificial Neural Networks (ANN). Thereby, the impressive success is tightly coupled with the development in CPU and GPU clusters of ever increasing capabilities. From the perspective of algorithmic development, the focus was set on improvements in the quality of results. For specific and well constrained test cases, human capabilities are nowadays achieved or even surpassed with best performing examples. However, further progress will rely on improved efficiency in the computations to enable dynamic learning in real-time. For this to happen the energy per operation has to be reduced and faster convergence during learning is necessary. Besides the design of flexible accelerators, the chair entertains a close cooperation with other experts in the domain of algorithmic development in order to shed light on all aspects of the design space in a quantitative manner.