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     Dr. Leticia M. Bolzani Pöhls
     Senior Researcher at IDS
     at RWTH Aachen University


     IDS (seminar room UMIC-25) and
     zoom (contact This email address is being protected from spambots. You need JavaScript enabled to view it.)


    Oct. 4th, 2022 at 2pm
    Oct. 18th, 2022 at 2pm
    Dec. 6th, 2022 at 2pm.



During the last 50 years, CMOS technology has been scaled down according to Moore's Law, making the implementation of high-performance applications possible. However, there is a growing concern that device scaling will become infeasible below a certain feature size. The scaling roadmap for integrated circuits was extrapolated from the current Moore's Law regime into the following three main domains: (1) More Moore, (2) Beyond CMOS, and (3) More than Moore. Independent on the domain, integrated circuits are susceptible to manufacturing and time-dependent deviations that compromise their quality and reliability. The proposed lectures aim to address reliability issues in integrated circuits after manufacturing as well as during lifetime. In more detail, a background related to test theory will be provided and the main challenges and solutions related to manufacturing testing and fault tolerance strategies will be summarized. Finally, the third lecture provides an overview of the main challenges related to testing Resistive RAMs after manufacturing and summarizes the solutions for avoiding test escapes.

Third lecture (December 6th, 2022) :

Testing RRAMs: Challenges and Solutions Memristive devices represent promising candidates to complement and/or replace CMOS technology due to their CMOS manufacturing process compatibility, great scalability, high density, zero standby power consumption as well as their capacity to implement high density memories and new computing paradigms. Despite these advantages, memristive devices are also susceptible to manufacturing deviations, defects and process variation, that may cause unique faulty behaviors that are not seen in CMOS, significantly increasing the complexity of test strategies. In this context, this talk aims to provide an overview of possible manufacturing deviations, their faulty behavior as well their impact on the reliability of Resistive Random-Access Memories (RRAMs) during lifetime. As final topic, I will summarize the state-of-the-art related to manufacturing test strategies, including aspects related to the use of stress conditions to facilitate the fault detection.


Throughout her career specific test and reliability regarding integrated system design as well as varying novel technologies have been her focus. She studied in Prof. Matteo Sonza Reorda's CAD Group (Politecnico di Torino, Italy), developing test and fault tolerance strategies for safety-critical applications and concluded her PhD entitled “New Techniques for Highly Reliable Systems-on-Chip (SoCs)” in 2008. She decided to research new low power design strategies during a post-doctoral fellowship with Prof. Enrico Macii's EDA Group (Politecnico di Torino, Italy) and proposed strategies to reduce dynamic and leakage power of integrated circuits, including the development of a Electronic Design Automation (EDA) tool. Back in Brazil her research shifted to Hardware and Software Strategies for the Design of Electromagnetic Interference- and Radiation-Aware Systems-on-Chip (SoCs). From 2010 to 2022 she was associate professor at Pontificial Catholic University of Rio Grande do Sul (PUCRS) and worked on other key subjects related to CMOS technology scaling and to develop new test methodologies for detecting weak resistive-defects in CMOS SRAMs. In 2013 she tackled emerging technologies enabling the further downscaling of integrated circuits and returned to the EDA Group studying graphene-based devices as a post-doctoral fellow. Her broad knowledge, the constant discussion and collaboration with national and international research partners made her focus on the development of test and fault tolerance solutions for nanoscale integrated circuits. Currently she is a senior researcher at IDS (RWTH University, Germany) working on the development of manufacturing test and fault tolerance strategies for memristive device-based systems. Among other activities, she continues to serve as technical committee member in many IEEE-sponsored conferences, such as IEEE DATE, IEEE IOLTS; IEEE ETS, VLSI-Soc. She is member of the IEEE Latin American Test Symposium Steering Committee and of the Biannual European - Latin American Summer School on Design, Test and Reliability (BELAS) Steering Committee as well as Coordinating Editor of Journal of Electronic Testing: Theory and Application.