The lab is conducted in English.
Procedure
The lab covers the following topics:
- Introduction to the hardware description language SystemVerilog
- Introduction to reconfigurable hardware components and FPGAs
- Introduction to FPGA design flow, Vivado, IP-based design, High-Level Synthesis (HLS)
- Implementation of basic logic circuits, counters, state machines etc. on FPGAs
- Implementation of a keyword spotting system
Next date
every semester
Registration
Registration is possible via RWTHOnline.
For capacity reasons, the number of participants for this lab is limited.
Introduction
Preliminary information on the FPGA design lab in WS 2025/26:
14/10/2025: 10:00 a.m., UMIC (2165|024).
Participation in this event is mandatory.
Contact
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