Talking language is german.

Procedure

The lab covers the following topics:

  • Introduction to the hardware description language Verilog
  • Introduction to reconfigurable hardware components (Field Programmable Gate Array, FPGAs)
  • Introduction to the design flow with FPGAs
  • Implementation of basic logic circuits, counters, state machines etc. on FPGAs
  • Implementation of a radio clock receiver (DCF 77) based on a FPGA board
  • Filter implementation for real-time video signal processing

Next date

every semester

Registration

Registration is possible via RWTHOnline.

For capacity reasons, the number of participants for this lab is limited.

Introduction

Preliminary information on the FPGA design lab in WS 2021/22 is given according to current planning, until further notice and depending on the Corona regulations on 18/10/2021, 9:30 a.m., as a Zoom-Meeting.

Participation in this event is mandatory.

Contact

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Informations in RWTH Online