Talking language is german.
The lab covers the following topics:
- Introduction to the hardware description language Verilog
- Introduction to reconfigurable hardware components (Field Programmable Gate Array, FPGAs)
- Introduction to the design flow with FPGAs
- Implementation of basic logic circuits, counters, state machines etc. on FPGAs
- Implementation of a radio clock receiver (DCF 77) based on a FPGA board
- Filter implementation for real-time video signal processing
Registration is possible via RWTHOnline.
For capacity reasons, the number of participants for this lab is limited.
Preliminary information on the FPGA design lab in SS 2022: 05/04/2022: 15:00-18:00 p.m., Mies-van-der-Rohe-Str.15 Room 326.
A deposit of 100€ is needed for the FPGA hardware. Please bring this to the meeting. Please wear a face mask.
Participation in this event is mandatory.