Procedure
The lab covers the following topics:
- Introduction to the VLSI-CMOS-design environment
- Design of typical CMOS basic circuits ( e.g. NAND gates)
- Logical verification, DRC and LVS
- Circuit simulation to determine the critical time and power loss
- Automated implementation of a microprocessor logic
- Implementation of optimized basic cells (e.g. full adders)
- Generation of complex circuit components by automated placement and wiring of the basic cells
- Introduction to the standard cell - design flow
Next date
every semester
Registration
Registration is possible via RWTHOnline.
For capacity reasons, the number of participants for this lab is limited.
Introduction
Preliminary information on the lab in SS 23 is held on 6/4/2023, 10:00 a.m. at seminar room UMIC 025 (2165|025)
Access data for the videoconference in case of online or hybrid mode will be announced in RWTH-Moodle or via e-mail. Participation in this preliminary meeting is mandatory.
Contact
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