The chair introduces its research into practical use cases to demonstrate their feasibility in a real-world context. With its expertise ranging from highly optimized classical digital processing components to disruptive technological inventions in custom design such as compute-in-memory (CIM) architectures, the objective is to apply this knowledge into common DSP applications in a secure and reliable manner.
[C. Lanius et al., “Automatic Generation of Structured Macros using Standard Cells – Application to CIM,” ISLPED, 2023]
[C. Lanius et al., “Multi-Function CIM Array for Genome Alignment Applications built with Fully Digital Flow,” NorCAS, 2022, doi: 10.1109/NorCAS57515.2022.9934470 , pdf]
Channel Decoder
Channel decoder are used for error detection and correction in various domains. One example is the high-throughput digital (wireless and wireline) transmission channels. Another one is found as key component of modern storage systems. The challenges are two-fold: on one side is the high computational throughput requirement, on the other side is the constraint on available area and acceptable cost. This is especially true Turbo- and Low-Density-Parity-Check-Codes with transmission rates close to the fundamental Shannon limit.
System-on-Chip-components for Multi-Radio support
Today, devices for wireless communication are required to support multiple standard simultaneously (such as GSM, UMTS, LTE, WLAN, BT, GPS) in order to limit the system integration complexity and cost. Classic highly optimized SoCs are not meeting these requirements anymore – especially in view of evolving standard within the lifetime of a product. The so-called “Software Defined Radio” concept offers such flexibility but poses enormous requirements on the available performance and communication bandwidth between the required, highly-parallel processing units realized in “Single Instruction Multiple Data” (SIMD) architectures. Here, flexible accelerators offer key advantages. Suitable micro-architectures and concepts for implementation are developed at the chair targeting low-power, area efficient arithmetic units. This includes macros for ‘Fast-Fourier-Transforms’ (FFT) and static (non-volatile) memories of small to medium capacity as required for such processing units.