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     Prof. Dr. Abhijit Chatterjee
     Full Professor in SCSE
     at Georgia Tech


     IDS (seminar room UMIC-25) and
     zoom (contact Diese E-Mail-Adresse ist vor Spambots geschützt! Zur Anzeige muss JavaScript eingeschaltet sein.)


    Dec. 13th, 2022 at 2pm.




The reliability and security of deep neural networks (DNNs) is of great concern due to their widespread use in data-intensive applications. Ensuring the same is made difficult due to the typically large numbers of neurons in such systems and the complex relationship between errors in computation and their effects on network performance accuracy. In this talk, we study the problem of designing error-resilient DNNs where errors can stem from: (a) soft errors in computation of matrix-vector multiplications and neuron activations, (b) malicious trojan and adversarial security attacks and (c) effects of manufacturing process variations on analog crossbar arrays that can affect DNN accuracy. The core principle of error detection relies on internal state space encodings of the DNN input, hidden and output layers. This makes use of prior results in the domain of algorithmic checksums widely used for error detection in linear signal processing application. A key contribution is in adapting such checking techniques to the inherent nonlinearity of neuron computations with minimal impact on error detection coverage. Once errors are detected, they are corrected using probabilistic methods due the difficulties involved in exact diagnosis of errors in such complex systems. The technique is scalable across soft errors as well as a variety of security attacks. The effects of manufacturing process variations are handled through the use of compact tests from which DNN performance can be predicted using nonlinear regressors. Experimental results on a variety of test cases are presented to demonstrate the viability of the proposed techniques.


Abhijit Chatterjee is a Professor in the School of Electrical and Computer Engineering at Georgia Tech and a Fellow of the IEEE. He received his Ph.D in electrical and computer engineering from the University of Illinois at Urbana-Champaign in 1990. Dr. Chatterjee received the NSF Research Initiation Award in 1993 and the NSF CAREER Award in 1995. He has received seven Best Paper Awards and three Best Paper Award nominations. His work on self-healing chips was featured as one of General Electric's key technical achievements in 1992 and was cited by the Wall Street Journal. In 1995, he was named a Collaborating Partner in NASA's New Millennium project. In 1996, he received the Outstanding Faculty for Research Award from the Georgia Tech Packaging Research Center, and in 2000, he received the Outstanding Faculty for Technology Transfer Award, also given by the Packaging Research Center. In 2007, his group received the Margarida Jacome Award for work on VIZOR: Virtually Zero Margin Adaptive RF from the Berkeley Gigascale Research Center (GSRC). Dr. Chatterjee has authored over 450 papers in refereed journals and meetings and has 22 patents. He is a co-founder of Ardext Technologies Inc., a mixed-signal test solutions company and served as chairman and chief scientist from 2000-2002. His research interests include error-resilient machine learning, signal processing and control systems, mixed-signal/RF/multi-GHz design and test and adaptive real-time systems.