Speaker
Dr. Christian Lütkemeyer
Founder, PIX-EDA LLC
Location
IDS (open space, top floor)
Online participation on request:
Date
July 1st, 2025 at 2 pm.
Background
The world is on a catastrophic path of accelerating fossil fuel use and CO2 emissions increase. Artificial Intelligence data centers are projected to require new sources of electric power on a scale of hundreds of 1GW power plants in a few years. The paradigm shift from a shared regulator for many lower power chips to dedicated regulators for kW-scale SOCs opens significant power saving opportunities when optimized Adaptive Voltage Scaling (AVS) technology is leveraged. A holistic optimization of digital implementation and timing sign-off for SOCs with AVS provides significant resource-saving opportunities on the design and energy demand side. Standardization in this complex optimization space can enable successful co- development of critical IP and risk reduction for the AI SOCs of the future while significantly reducing CO2 emissions and the energy cost of future AI data centers.
Energy-savings of 20% are easily achievable for digital circuits by right-sizing the supply voltage to the actual temperature and speed of the individual SOC. Pushing digital supply voltages down to the 0.5V level can reduce power by 50% compared to nominal supply voltages of 0.75V.
Outline
Starting from a brief look at well-established standards at the foundation of timing modeling for digital timing sign-off, the seminar highlights the pivotal transition from standardized, fixed supply voltage schemes of the past - where many ICs shared a single power supply - to a new reality - where many power switches must be combined to deliver kilo-Amperes of current to feed kW-scale Artificial Intelligence SOCs for the Gigawatt AI datacenter of the future. A look at a basic supply partitioning concept of a SOC with Adaptive Voltage Scaling, and performance trends of digital logic over process, voltage, and temperature set the stage to introduce a streamlined AVS timing anchor methodology that leverages the closed loop control of the switching speed on the SOC to eliminate dominant sign-off corners in the traditional timing sign-off methodology.
The seminar discusses the highly artificial nature of interconnect modeling on integrated circuits and proposes a typical, manufacturing target-based modeling scheme with calibrated margin that enhances the timing robustness at small insurance cost while significantly reducing the design complexity.
Interconnect capacitance ratio measurements are proposed to provide detailed insights into the capacitance variations across different metal layers during manufacturing and for individual SOCs.
The concept of performance-bounding AVS replica circuits and critical aspects for their implementation and use will be discussed.
We highlight how commercial Power Integrity (PI) tools apply severe model simplifications for the demand currents of switching CMOS circuits to provide very limited data for the worst-case supply drop of complex digital circuits. Understanding these limitations provides the background to appreciate the substantial value that supply drop measurement circuits can provide when system operators want to right-size the supply voltage for individual SOCs.
Low-latency digital clock distribution is important to minimize clock insertion delay and associated margins. We present a standardization proposal for a matched-driver, MAD-Clock circuit and clock rail scheme that embraces increased inductance to reduce power and at the same time avoids the need to model on-chip transmission lines and their inductance explicitly.
Biography
Christian Lütkemeyer founded PIX-EDA LLC in 2024 with the vision of sharing essential knowledge in the holistic design of low-power, high-performance digital system-on-chips (SOCs). The mission: Sharing knowledge can save power and large-scale CO2 emissions.
Prior to founding PIX-EDA, he served as a Senior Distinguished Engineer at Marvell Technology Inc., where he focused on methodologies for creating top-tier SOCs in the coherent-optical transceiver space. Christian joined Marvell through its acquisition of Inphi Corporation in 2021. Inphi had previously acquired ClariPhy Inc. in December 2016. He had joined ClariPhy in February 2016, bringing with him over 16 years of experience from Broadcom Corporation's Office of the CTO. There he led the Timing Sign-Off Center-of-Excellence at his departure after an exciting journey that started in 1999 with the custom digital implementation of DSP algorithms for Gigabit Ethernet transceiver chips.
At PIX-EDA, Christian is focused on developing technology to assess silicon performance and measure supply voltage variations, while advocating for holistic implementation and timing sign-off strategies aimed at resource-efficient SOC development with AVS.
He is inventor or co-inventor of 18 patents and obtained his Dr.-Ing. degree from Aachen University of Technology in Germany.